J.C. Manifacier
Université de Montpellier, France

Semi-insulating III-V semiconductors obtained by deep level compensation are often used in the fabrication of solid state devices (as in metal semiconductor field effect transistors). This paper presents some new results in regard to 1D and 2D numerical simulation of PIN GaAs structures, and examines the effects of a gradient in the deep-level capture cross section on electron and hole transport.