Raminderpal Singh
Cadence Design Systems

As levels of IC integration continue to rise, more and more analog blocks are being integrated onto the same silicon as digital ASIC designs. The integrated analog blocks may not be the highest performing, due to factors such as process requirements and signal integrity problems; however, it is very common for previously separate analog ICs to now be designed as IP blocks specifically for integration.

This paper adopts the designer's perspective, describing the problems confronted and outlining the challenges and solutions available.