Stephen Bailey et al.
Mentor Graphics

This paper describes the basic elements of low power design and verification and discusses how the Unified Power Format (UPF), along with innovative techniques, enable power-aware verification at the register transfer level (RTL), using traditional RTL design styles and reusable blocks. The result is a multi-tool solution that can be used throughout the RTL-to-GDSII flow, applying consistent semantics for both verification and implementation.