Shiv Balakrishnan and Chris Eddington
Synplicity

This white paper discusses the challenges and requirements of creating portable algorithmic IP for field programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). It illustrates how an ESL synthesis methodology using Synplicity's Synplify digital signal processing (DSP) tool — which automatically creates optimized and synthesizable real-time logic (RTL) implementations — can significantly reduce the time and effort required to implement either technology. An example of a basic DSP building block, a 65-tap FIR filter, is used to describe the process for implementation-aware logic synthesis and design exploration.