Te Hung Wu et al.
Mentor Graphics and United Microelectronics

Overlay variations between different layers in integrated circuits fabrication can result in poor circuit performance. Even worse, they can cause circuit malfunction and consequently affect process yield. Searching for interconnects hot spots should therefore include overlay variations. The accuracy of inclusion of the overlay variation effect comes at the expense of a more complex simulation setup. Many issues must be taken into consideration, including runtime, process combinations to be considered, and the feasibility of providing a hint function for correction.

In this paper, we present a systematic approach for classification of interconnects durability through the lithographic process, taking into account focus, dose, and overlay variations.