Cadence Design Systems

In recent years, power consumption has moved to the forefront of digital integrated circuit (IC) development concerns. The combination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth in power density. Furthermore, with every new process generation, leakage power consumption increases at an exponential rate.

This paper introduces the various aspects of power-aware design during chip/system architectural specification, power architecture definition, design, physical implementation, and verification.