Laurence Cooke
eASIC

As we move to multi-million gate chips, it has become necessary to adopt design reuse strategies for these new SoCs. At the same time, increasing metal layers and shrinking mask lithography has increased the NRE costs above $1/2 million per prototype. This has eliminated the traditional gate array technology as a viable option. Some experts have suggested the functional variation required to these chips can be done with software or FPGA, but the former has performance limitations and the latter requires too much silicon area. Another alternative, a single metal mask programmable interconnect with SRAM-based programmable logic, 50K gate core, is presented. The interconnect programming provides a low NRE option for configuration, with performance closer to Standard Cell, to fill the gap vacated by gate arrays. This paper describes the structure and features of these new cores and explores their use within a SoC platform-based design environment.