Altera

Bandwidth-intensive applications such as controller buffer memory, look-up tables (LUTs) and linked lists require the maximum memory bandwidth possible. The QDR II+ and QDR II memory architecture features separate read and write ports operating twice per clock cycle to deliver a total of four data instructions per cycle.

Stratix III I/Os are specifically designed to support double data rate (DDR) external memory standards such as QDR II+ and QDR II SDRAM. Up to 31 embedded hard I/O registers are found behind each DQ pin for rapid integration and safe transfer of data to and from the memory domain to application domain. Frequencies of up to 350 MHz or 1,400 Mbps are supported on the top and bottom I/O banks, with lower speed support on the side I/O banks.