George Kuo
Cadence

The need to save power-while maintaining performance goals at 90- and 65 nanometers creates challenges in design and test that necessitate deep collaboration among key members of the design chain-foundries, EDA companies, and IP suppliers. In the second phase of the power management methodology, TSMC, ARM and Cadence validated interdependent technology for low-power design and continues to explore additional opportunities to reduce power consumption. Meanwhile, a shared knowledge of design requirements up and down the design chain helps to ensure that the design can be reliably manufactured. This type of close collaboration has enabled the SDC team over the past two years to consistently drive down power consumption and to validate, through proof point projects, important new techniques in power management, DFT, and low-power formal verification.

In this second phase of the low-power project, the SDC developed and enhanced a version of its power management methodology and proved it through the tapeout phase of the ARM1136JF-S processor design. On top of the significant reduction in power consumption achieved in Phase I, this proof point design showed that through effective power gating techniques, leakage power can be reduced by 98.5 percent in selectively isolated circuitry.