M. Rahmati and M.R. Rozeh Rezvani
Amikabir University of Technology, Iran
A systolic array architecture for computing output power of MVDR (minimum variance distortionless response) beamformer is described. Presented architecture is utilizable for direction of arrival estimating systems. It's fully pipelined and based on recursive orthogonal triangularization. Simulating using VHDL shows good results.
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