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Optimizing Performance of DSP Systems through Block-Level Design

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2005 Embedded Systems Conference San Francisco Paper
59 KB (7 pages)
March 10, 2005
 

Thomas M. Cesear
AccelChip

While experienced software developers and system designers are familiar with software implementations of algorithms, they often struggle to adapt to the requirements of silicon implementation. Using high-level languages like MATLAB makes it easy to develop new algorithms, but design teams still struggle to determine which micro-architecture for key functions are the most effective and efficient for a specific design. Even the implementation of a function as simple as a square root can have a dramatic effect on the noise, area, and frequency of the entire system. This paper describes the benefits of alternative architectures and micro-architectures for key DSP building blocks such as FFT/IFFT, math functions, and forward error correction in terms of throughput, latency, power, noise, frequency, and area and how tools can automate this tradeoff analysis.

 
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AccelChip
Embedded Systems Conference (ESC)
   

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