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Implementation Techniques for DSP Algorithms on Parallel Architectures

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1999 International Conference on Signal Processing Applications and Technology (ICSPAT) Paper
47 KB (16 pages)
November 2, 1999
 

Rajeev Kumar, Udayan Bhawnani, Sameer Sawarkar, and Rishikesh Basu
Motorola India Electronics

Digital signal processing is one of the fastest changing fields in the semiconductor industry today. Like earlier advances in microprocessors and computer memories, digital signal processing is a foundation technology and is capable of transforming broad areas of the electronics industry. Its impact is being felt in a broad range of applications, including cellular phones, modems, personal computers, stereo systems, cars, and Internet access devices.

The advances in technology have also resulted in parallel architectures, leading to manifold improvement in the performance. Advent of parallel architectures has forced us to go back and re-look at the algorithms from a parallelization perspective. The extent of parallelization of the algorithm, of course, depends on the kind of architecture we have available with us, as well as the algorithm itself.

In this paper, first we introduce some generic features of Digital Signal Processor (DSP) architectures. Then, we look at classification of parallel architectures, followed by a revisit to the generic features of DSP with a parallelization point of view. Some techniques for implementing the standard C algorithms on a parallel architecture will also be introduced. These are algorithms, which occur frequently in DSP applications. While parallelizing the DSP algorithms, a few points have to be kept in mind. We will take a look at some of them.

 
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ICSPAT
Motorola Computer Group (MCG)
   

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