PLX Technology

The PEX 8311 is a bridge from a low overhead parallel generic local bus, used by various processors, DSPs, memory, and FPGA designs, to a PCIe port. In this conversion, the bridge completely translates data from the local bus into PCIe packets with full packet header generation. Address spaces from the local bus and PCIe domain are fully translated. Out-of-band signals on the local bus are translated into message signaling interrupt (MSI) packets and vice versa. The bridge supports all transaction types. Full on-chip buffers provide flow control and the link layer CRC ensures data integrity.