George Kuo
Cadence Design Systems

The mission of the Silicon Design Chain Initiative (SDC), an effort of Applied Materials, ARM (including its Artisan ARM Physical IP group), Cadence and TSMC, is to optimize the silicon design chain. The Initiative asserts that in our disaggregated market, the entire industry must join together to solve pressing problems.

The initiative chose as its first task a low-power design-through-manufacturing flow. The partners in this project were ARM, Cadence and TSMC. The collaborators selected to implement an ARM1136JF-S processor and related circuitry in a standard 90-nanometer CMOS process. ARM contributed the processor core and the Artisan physical libraries and validated the silicon. Cadence implemented the chip, through a low-power design methodology that used version 4.1 of the Encounter digital design platform. TSMC contributed the process and fabricated the test chips, which were functional at first silicon. This resulted in an eventual 40 percent power savings as compared to a timing closure baseline implementation of the same ARM1136JF-S based chip.