Andy Nightingale, John Pierce
ARM and Cadence Design Systems

There is little argument today that when SoC designers look across their development cycle, the greatest obstacle they see to improving efficiency and shortening time-to-market is system verification. The growing complexity of designs, their rising software content, relentless performance increases, and the complex interaction of functional blocks are all contributing to the problem.

The key to improving designer productivity is reducing the amount of time designers spend in test creation and design verification, which can be done with extensive reuse of components and tests. This article will explore a new methodology for reuse and scaleability of SoC components and tests. It will highlight the key components in this new verification methodology and how design teams can use the SystemC verification library to take advantage of this new approach to verification reuse.