Robert Taft, Chris Menkus, Maria Rosaria Tursi, Ols Hidri, Valerie Pons, and Paul McCormack
National Semiconductor

This paper demonstrates the significant conversion speed achieved for an 8-bit ADC using folding with interpolation and averaging when small, calibrated amplifiers are used. Various ADC architectures are briefly discussed and the chosen folding architecture with calibration is explored in more detail. Following this explanation, the performance summary is presented along with some typical applications.