Design Verisity

Due to the increasing complexity of today's ASICs and systems, functional verification has become a major bottleneck in the design process. Design teams reportedly spend as much as 50 to 70 percent of their time and resources on the functional verification effort. This paper presents a new methodology for functionally verifying systems and ASICs—spec-based verification—an automated and measurable approach to verification that enables more effective verification methodologies while cutting the overall resource investment in half.