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	Title		Author/Company		Published
	Visualizing, Analyzing and Debugging SystemVerilog Testbench Environments		Bindesh Patel et al SpringSoft and Verilab		Apr 2009 White Paper
	Using SystemVerilog Assertions in Gate-Level Verification Environments		Mark Litterick Verilab		Jun 2008 White Paper
	An Introduction to Aspect Oriented Programming in e		David Robinson Verilab		Jun 2006 White Paper
	Pragmatic Simulation-Based Verification of Clock Domain Crossing Signals and Jitter Using SystemVerilog Assertions		Mark Litterick Verilab		Feb 28, 2006 White Paper


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