|
Title |
|
Author/Company |
|
Date/Type |
| |
The TSMC Tsunami at DAC 2009
|
|
Peggy Aycinena
| |
Jul 28, 2009
|
| |
Clock mesh variation robustness: benefits and analysis
|
|
Mallik Devulapalli and Yuichi Kawahara, Synopsys Inc.
| |
Jun 29, 2009
|
| |
The Virtual Vehicle: Part 3 - Developing robust wiring harnesses
|
|
Thorsten Gerke and Stefan Lagerqvist, Synopsys
| |
Mar 12, 2009
|
| |
The Virtual Vehicle: Part 2 - Early validation of vehicle electrical systems and power management
|
|
Thorsten Gerke, Synopsys
| |
Feb 13, 2009
|
| |
The Virtual Vehicle: Part 2 - Early validation of vehicle electrical systems and power management
|
|
Thorsten Gerke, Synopsys
| |
Feb 13, 2009
|
| |
The Virtual Vehicle: Part 1 - In-vehicle networking simulation and analysis
|
|
Thorsten Gerke, Synopsys
| |
Jan 09, 2009
|
| |
Synopsys unveils new IC compiler router
|
|
Gabe Moretti
| |
May 27, 2008
|
| |
The DFM melting pot
|
|
Gabe Moretti
| |
May 22, 2008
|
| |
Design for low-power manufacturing test
|
|
Chris Allsup, Synopsys, Inc.
| |
Mar 18, 2008
|
| |
Design for low-power manufacturing test
|
|
Chris Allsup, Synopsys, Inc.
| |
Mar 18, 2008
|
| |
Synopsys accelerates circuit simulation performance
|
|
Gabe Moretti
| |
Mar 10, 2008
|
| |
Low Power Design For Analog/Mixed-Signal IP
|
|
Navraj Nandra, Synopsys
| |
Mar 04, 2008
|
| |
Complex SoC testing with a core-based DFT strategy
|
|
Sandeep Kaushik, Synopsys and Paul Policke, Qualcomm
| |
Feb 26, 2008
|
| |
Applying Constrained-Random Verification to Microprocessors
|
|
Jason C. Chen, Synopsys Inc.
| |
Dec 10, 2007
|
| |
Tech Tutorial: How to design an FPGA from scratch
|
|
Sven Andersson, ZooCad Consulting
| |
Aug 29, 2007
|
| |
Software-intensive ASICs/ASSPs demand integrated prototyping
|
|
Andrew Haines, Synplicity
| |
Jun 22, 2007
|
| |
DAC—Variations on a Theme
|
|
Jim Lipman
| |
Jul 06, 2005
Commentary |
| |
2005 will be the Year of SystemVerilog Tool Announcements
|
|
Michiel Ligthart
Verific Design Automation
| |
Jan 11, 2005
Electronics Engineering Trends in 2005 Series |
| |
Less is More for DAC 2004
|
|
Jim Lipman
SemiView
| |
Jul 06, 2004
Director's Choice |
| |
EDA Tools Bolster Chip Recovery
|
|
Jim Lipman
SemiView
| |
May 26, 2004
Commentary |
| |
In Design Closure, Timing Isn't Everything
|
|
Jim Lipman
TechOnLine
| |
Jul 15, 2002
Commentary |
| |
Complete SoC Design, Verification Reign at DAC Exhibits
|
|
Jim Lipman
TechOnLine
| |
Jun 07, 2002
Commentary |
| |
Analog Synthesis: Ready for Prime Time?
|
|
Jim Lipman
TechOnLine Content Director
| |
Apr 10, 2002
Commentary |
| |
EDA Executives High on Industry Outlook
|
|
Jim Lipman
TechOnLine
| |
Feb 05, 2002
Director's Choice |
| |
ITC 2001 Emphasizes More Cooperation, Less Test Cost
|
|
Jim Lipman
TechOnLine Content Director
| |
Nov 08, 2001
Commentary |
| |
DAC Revisited—Low Attendance, High Technology
|
|
Jim Lipman
TechOnLine
| |
Jul 02, 2001
Commentary |
| |
Design Languages for Embedded Systems
|
|
Stephen A. Edwards
Synopsys
| |
May 18, 2001
OSEE Article |
| |
To Chip Designers, Test is a Four-Letter Word
|
|
Jim Lipman
TechOnLine
| |
Mar 19, 2001
Commentary |
| |
A View from the Top of the EDA Mountain
|
|
Jim Lipman
TechOnLine
| |
Mar 17, 2000
Commentary |
