The increasing miniaturization of advanced microelectronics drives the magnitude of charge representing information within a circuit to increasingly smaller levels, raising the susceptibility of its corruption by spurious signals. Noise spikes caused by the stochastic collision of energetic single particles with charge-sensitive regions at the semiconductor surface can destroy stored information, leading to logic errors. Error-producing single particles for highly advanced microcircuits are omnipresent, emanating from a variety of sources, from an alpha particle emitted from the metal layers forming the interconnect grid on the circuit to galactic high energy heavy ions encountered by the microelectronics within satellite systems. No matter the source of the ions, the resulting excess charge collection dynamics that may lead to logic errors are in all cases essentially the same. That is, if the interaction of an ion with the semiconductor substrate occurs in close proximity to the data node of a latch circuit, the resultant excess ionization charge collected at the data node may cause the latch to erroneously change state, a single-event upset (SEU). The information now contaminated by this invalid data state is in some cases unrecoverable. Consequently, a considerable amount of effort is spent during the circuit library design and development phases to minimize the probability of occurrence of SEU's. Complementary Metal Oxide Semiconductor (CMOS) technologies are predominantly used to build the most advanced high-performance, low-power digital systems and quite a number of SEU hardening design techniques have been developed to mitigate the threat of logic upset due to energetic particles. This tutorial will describe in much greater detail the threat posed to the information stored in CMOS data latches by energetic ion strikes. Some of the most commonly used design-hardening approaches will be examined and the relative merits of each approach will be explored.