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Demystify MIPI M-PHY Receiver Physical Layer Test Challenges

Original Air Date: Aug 13, 2013 | Duration: 60 minutes Webinar
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Overview:
The Mobile Industry Processor Interface (MIPI) Alliance standards body standardizes interfaces for mobile designs. The MIPI D-PHY and M-PHY are introduced as high-speed physical layers serving as base for multiple applications such as camera, display, memory and baseband running protocols such as CSI, DSI, UniPro, LLI and DigRFv4. Other, originally non-mobile, protocols such as USB 3.0 and PCIe are being adapted to work with the M-PHY physical layer as well. Being optimized for both performance (high data rates) and (low) power consumption introduces many new validation (test) challenges outlined in the MIPI Conformance Test Suites (CTS), which are key to system interoperability. M-Phy Rev. 1,2 & 3 currently support data rates at ~1.5 ~3 and ~6Gbps respectively featuring transmit de-emphasis and requiring receiver testing with a complex jitter cocktail. Work on M-PHY specification rev.4 has been started adding Gear 4 support (~12 Gbps data rate). If you are developing or validating these MIPI-M-Phy based RX designs (and /or are a silicon / IP vendor or system integrator), you'll want to attend this seminar to understand how to overcome the physical layer test challenges.

Who should attend:
Design, test and validation engineers who need to characterize and validate compliance of their MIPI designs.

Presenters:
Michael Fleischer-Reumann, Expert Product Marketing Engineer, Agilent Technologies
After receiving his Diploma in Electrical Engineering from the Ruhr University of Bochum, Germany, Michael joined HP in 1980 as an R&D engineer for Pulse generator HW designing discrete and integrated output stages. He then became Project leader for HPs 1st optical average power meter, attenuator and OTDR. Back at HP's line of logic signal sources as an R&D project manager he lead the development of HP's 1st data generator-analyzer system for physical layer test, 1st multiple serial BERT and initiated the 1st Parallel BERT as a strategic product planner. His technical work resulted in several patents related to fiber optic components, electronic circuits and measurement methods. For an eight year period he lectured electronics at the Stuttgart "Berufsakademie", a college for Diploma Engineers (BA). Today, besides his strategic planning work he's active in standardization, with contributions within PCI-SIG, IEEE, OIF and Mipi; momentarily his main technical interest is the field of signal integrity and receiver jitter tolerancing.

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