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Overcome High Speed Digital Design Challenges: Part 3 - What on Earth is Jitter Amplification, and Why Should I Care?

Original Air Date: Apr 9, 2013 | Duration: 60 minutes Webinar
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Overview:
High speed digital chip-to-chip link performance is often limited by jitter in the multigigabit per second regime. It is a surprising fact that jitter can actually be amplified by a lossy channel even when the channel is linear, passive, and noiseless. In this webcast we will cover the basics of jitter amplification and show you how to accurately analysis the effect in your system using ADS Channel Simulator.

Who should view this webcast:
Signal integrity engineers and high speed digital engineers of multigigabit links who are running into effects previously only seen in RF and microwave circuits.

Presenter:
Fangyi Rao, Master R&D Engineer, Agilent Technologies

Fangyi Rao received his Ph.D. degree in physics from Northwestern University in 1997, for research in quantum theory of magnetism and transport. He joined Agilent EEsof in 2006 as a Senior Development Engineer, where he works on Analog/RF simulation technology in ADS and RFDE. From 2003 to 2006 he was with Cadence Design Systems, where he made key contributions to the company's Flexible Balance technology and perturbation analysis of nonlinear circuits. Prior to 2003 he worked in the areas of EM simulation, nonlinear device modeling, and optimization.

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