The Vivado Design Suite 2013.1—Accelerating Time to Integration and System-Level Design
Accelerating the development of smarter systems requires levels of automation that go beyond RTL level design. With the introduction of the Vivado™ Design Suite, Xilinx delivers a SoC-strength, IP-and system centric, next generation development environment that has been built from the ground up to address the productivity bottlenecks in system-level integration and implementation.
This webinar will explore the design methodologies and features of the Vivado Design Suite 2013.1 including the Vivado IP Integrator (IPI). Vivado IPI accelerates the integration of RTL, Xilinx® IP, third party IP and C/C++ synthesized IP. Based on industry standards such as the ARM® AXI interconnect and IP-XACT metadata for IP packaging, Vivado IPI delivers intelligent correct-by-construction assembly of designs co-optimized with Xilinx All Programmable solutions. Join us and learn this and more!
What attendees will learn:
- Latest release features of the Vivado Design Suite
- Inside the IP Integrator and enhanced HLS libraries
- How to learn more about the Vivado Design Suite
- Xilinx All Programmable device designers who want the latest information from Xilinx on the Vivado Design Suite
- New users of the Vivado Design Suite
- Those looking to migrate from the ISE Design Suite
Greg Daughtry, Senior Product Marketing Manager, Xilinx
Greg Daughtry holds the position of senior product marketing manager responsible for Vivado overseeing product requirements for the Interactive Design Environment (IDE), project infrastructure, Tcl scripting, and the placer, logic optimization, routing, and static timing analysis engines. He has over 19 years of experience in the hardware and software industries. Mr. Daughtry was most recently an ASIC design engineer developing advanced EDA tools methodology at Avago Technologies. Prior to that, he worked in the capacity of field sales and applications engineering at EDA startups Sierra Design Automation, which was acquired by Cadence and Monterey Design Automation, acquired by Synopsys. Both of these companies produced advanced EDA tools for ASIC floorplanning, placement, physical synthesis, routing, static timing analysis and verification. Prior to this, he worked at Intel as a full-customer circuit design engineer on multiple generations of leading-edge microprocessors and a signal integrity engineer for high-volume motherboards and chipsets. Mr. Daughtry also has worked at several startups a software engineer doing Graphical User Interface (GUI) design, enterprise peer-to-peer client/server transaction infrastructure, and industrial control and automation. He holds a B.S. in Electrical Engineering and a B.S. in Computer Engineering, and a M.S. in Computer Engineering, all from North Carolina State University.