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Case Study: Design and FPGA-Prototyping of an Application Specific Processor for Embedded Vision

Original Air Date: May 7, 2013 | Duration: 60 minutes Webinar
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Overview:
Computer vision algorithms are typically both compute-intensive and memory-bandwidth-intensive. Plus these algorithms are evolving quickly, calling for a software-programmable implementation. To achieve real-time performance while staying within the available power budget, application specific processors (ASIPs) are an alternative choice, as standard CPUs and GPUs often have to be ruled out for performance and/or power-efficiency reasons. When designing a processor-based SoC, FPGA prototyping is a key element in the design flow, as it allows HW/SW validation, real-time video inspection of the functionality, and debugging of memory interfaces often not captured during the simulation stages.

This webinar introduces Synopsys' Vision Processor Design and Prototyping solution, featuring Processor Designer and HAPS FPGA-prototyping. Using a real-world application-specific processor design example we will explain the steps needed to take the design from concept to final FPGA prototyping. This includes a discussion of typical pitfalls, shortcuts that turned into dead ends, best practices, and the value of pre-configured reference examples as starting point for your own design.

What will the audience learn:

  • Why application specific processors (ASIP) are suited for Embedded Vision applications
  • The steps it takes to move a processor design from concept to FPGA-prototyping implementation
  • Best practices how to debug at different stages of the design and prototyping flow
  • How the Synopsys Embedded Vision Processor Design Kit and the Synopsys HAPS FPGA prototyping solution can accelerate the design and prototyping stages
Who should attend:
  • Engineers looking for a prototyping solution for OpenCV-based vision applications
  • Computer architects who are working on complex real-time embedded vision systems and looking for ways to offload the computation intensive tasks from the main application processor
  • Processor designers who want to perform architectural analysis, with performance, power and area taken into account
Presenter:
Drew Taussig, Corporate Applications Engineer, Systems Group, Synopsys
Drew Taussig is a Corporate Applications Engineer in the Systems Group at Synopsys, supporting Processor Designer. Drew came to Synopsys from CoWare as part of the Processor Designer Product Team. Prior to CoWare, Drew led the ASIC Systems Architecture Team at Philips Semiconductors (now NXP). Drew has a Masters Degree in Electrical Engineering from Stanford University and a BS in Electrical Engineering and Computer Science from the University of Colorado at Boulder.

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