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Optimizing and Validating the Performance of Your AMBA®4 Interconnect

Original Air Date: Apr 25, 2013 | Duration: 60 minutes Webinar
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Overview:
A key concern for many companies is to ensure that their AMBA®4 interconnect-based multicore SoC will meet all of the performance requirements specified at the architectural level. This session will detail how customers are using Synopsys Platform Architect to drive performance criteria that can now be verified in the functional verification process through tight integration with Synopsys Verification IP for cache-coherent AMBA4 interconnect such as CCI-400.

Estimated length: 45 minutes + 15 minutes QA

Who should attend:
System Designers, SoC Architects, Verification Engineers, Verification Managers, and Project Managers

What attendees will learn:
In this session we will address the challenges associated with the performance of cache-coherent AMBA4 interconnects from two perspectives, using a case study illustration of a Server SoC:

  • How system architects can explore the architecture performance, power, and cost at a high level and traverse a huge parameter and application space to narrow down the architecture to a final specification that is being used for the RTL design.
  • How at the RTL verification stage – using next-generation verification IP and tools – not only the functionality of the final implementation is verified but also the actual performance of the RTL implementation is validated against the earlier architecture exploration results.
Presenters:
Neill Mullinger, Product Marketing Manager for Verification IP, Synopsys
Neill Mullinger is a product marketing manager at Synopsys for verification IP. Neill joined Synopsys in 2000 and has been focused on verification IP and protocol verification since 2002. He brings more than 25 years of experience in the hardware and EDA industries as an applications engineer and product manager.

Patrick Sheridan, Senior Staff Product Marketing Manager, Synopsys
Patrick Sheridan is responsible for Synopsys' system-level solution for multicore platform architecture design. In addition to his responsibilities at Synopsys, from 2005 through 2011 he served as the Executive Director of the Open SystemC Initiative (now part of the Accellera Systems Initiative). He has 28 years of experience in the marketing and business development of high technology hardware and software products and a BS in Computer Engineering from Iowa State University.

Tim Kogel, Solution Architect, Synopsys
Tim Kogel received his diploma and PhD degree in electrical engineering with honors from Aachen University of Technology (RWTH), Aachen, Germany, in 1999 and 2005 respectively. He has authored a book and numerous technical and scientific publications on electronic system-level design of multi-processor system-on-chip platforms. Today, he is working as a Solution Architect at Synopsys Inc. In this position, he is responsible for the product definition and future direction of Synopsys' SystemC-based Platform Architect product line.

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