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Logic Libraries for High-Performance, Processor-Based, Energy-Efficient SoCs

Original Air Date: Apr 2, 2013 | Duration: 60 minutes Webinar
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Overview:
Mobile communications, network servers, multimedia, and consumer SoCs must achieve the highest processor performance while consuming the minimal amount of energy. Logic libraries with a wide variety of high-performance flip-flops, clock tree cells and combinational cells provide an efficient method for optimizing CPU and GPU performance. Synopsys' multi-VT/multi-channel logic libraries and datapath libraries take advantage of high-performance, processor-optimized EDA tool flows, and enable SoC designers to achieve gigahertz performance within the constraints of aggressive power budgets.

In this webinar you will learn:

  • Ways to maximize system performance while managing power budgets of CPU, GPU, and other SoC blocks, each with different performance/power/area targets
  • How combining innovative power management techniques using multiple VTs/channel lengths in different SoC logic blocks delivers the optimal tradeoff in SoC watts per gigahertz
Length: 50 minutes + 10 minutes of Q&A

Who should attend: SoC design engineers, system architects, project managers

Presenter:
Ken Brock, Product Marketing Manager, Logic Libraries, Synopsys
Ken Brock is Product Marketing Manager for Logic Libraries at Synopsys and brings 25 years of experience in the field. Prior to Synopsys, Ken held marketing positions at Virage Logic, Simucad, Virtual Silicon, Compass Design Systems and Mentor Graphics. Ken holds a Bachelor's Degree in Electrical Engineering and an MBA from Fairleigh Dickinson University.

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