Designing with FinFETs

Overview:
FinFETs are emerging as the device of choice for 22-nm process nodes and beyond. They alleviate the leakage and the short channel bottlenecks seen in planar technologies, but they also introduce new design challenges for IP development, which require knowledge of and experience in designing with FinFETs to ensure design success. This webinar addresses the benefits and challenges of transitioning from planar to FinFET technologies and their implications for IP design.

This webinar will focus on:

• FinFET: the device - main features, differentiator from planar, attributes
• Designing with FinFETs - The opportunities and the challenges
• Reliability considerations for FinFETs

Length: 50 minutes + 10 minutes of Q&A

Who should attend: IP design engineers and SoC design engineers.

Presenter:
Jamil Kawa, Group Director, Solutions Group, Synopsys
Jamil Kawa joined Synopsys in 1998 and is currently a group director in the Solutions Group, working on advanced nodes technology development for memories and IP. He is also a member of the company's Technology Roadmap Team and Patent Committee. Jamil has held a variety of positions at Synopsys and has worked on DFM/DFY, 3-T SRAM technology, corrugated substrate technology (for FinFET manufacturing), low power design, and structured ASICs research. Jamil served as chairman of the Custom Circuits committee of CICC for 2005-2007. He holds seven issued patents and six pending patents in the areas of circuits and design architecture and has authored/co-authored over 20 papers and articles. Jamil holds a Master's degree in Electrical Engineering from the University of Michigan, Ann Arbor and an MBA from Santa Clara University. He holds 7 issued patents and 6 pending ones in the areas of circuits and design architecture and is the author / co-author of over 20 papers and articles.