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UBM Tech

10 ways to Debug your FPGA Design

Original Air Date: Feb 12, 2013 | Duration: 60 minutes Webinar
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Untitled Document Overview:
Learn how to cut FPGA debug time with more effective diagnosis of FPGA design setup and design specifications, and by identifying design errors en-masse in a single iteration. If you are an ASIC designer, learn techniques to more quickly make your design “FPGA friendly” to get working FPGA implementation on the board.


Speaker:
presenter photoAngela Sutton
Staff Product Marketing Manager, FPGA Implementation
Synopsys, Inc.

Angela Sutton brings over 22 years of experience in the field of semiconductor and semiconductor design tools to her role as staff product marketing manager for Synopsys, Inc. In this role, she is responsible for the FPGA Implementation product line.

Prior to joining Synopsys, Ms. Sutton worked as senior product marketing manager in charge of FPGA Implementation tools at Synplicity, Inc., which was acquired by Synopsys in May 2008. Ms. Sutton has also held various business development, marketing and engineering positions at Cadence, Mentor Graphics, Responsys, and LSI Logic. At LSI Logic she was responsible for marketing LSI Logic’s line of digital video semiconductor products and platforms.

Ms. Sutton holds a BSc. in Applied Physics from Durham University UK, and a PhD. in Engineering from Aberdeen University, UK.

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jakewestside Posted Apr 4, 2014

Hi. I used to follow the conventional techniques to debug the FPGA design. I had no idea about the other methods. OmniTech Support It looks relatively simple and less time consuming. I will surely try it out next time. Thanks a lot for sharing.

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