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Using Advanced Verification IP Capabilities to Accelerate Ethernet Verification

Original Air Date: Dec 11, 2012 | Duration: 60 minutes Webinar
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Overview:
This webinar will be based around a typical Ethernet switch design including a processor, switch fabric and Ethernet MACs. The Webinar will show how SystemVerilog, UVM and VIP are utilized to verify the Ethernet digital core and then integration of the core into the system. It will cover advanced VIP features including test suite and debug to accelerate productivity.

Speakers:
Neill Mullinger, Product Marketing Manager, Verification IP, Synopsys

Neill Mullinger is a product marketing manager at Synopsys for verification IP. Neill joined Synopsys in 2000 and has been focused on verification IP and protocol verification since 2002. He brings more than 25 years of experience in the hardware and EDA industries as an applications engineer and product manager.

Jaspreet Singh Gambhir, R&D Manager, Ethernet Verification IP, Synopsys

Jaspreet has more than 10 years of industry experience in front-end design and verification covering both block-level and SoC designs. He has worked on different phases of the ASIC design cycle, including architecture, design, verification, synthesis, timing and FPGA emulation. Jaspreet’s prior experience includes ownership of many multi-million gate count SoCs and sub-systems; developing designs and verification environments for Ethernet LANs, Wireless LANs, Packet Processing SoCs for NAS, WLAN AP and Printer Applications and Home Networking Technology MoCA. Today, he is working as an R&D Manager for the Verification IP (VIP) team at Synopsys and is responsible for Ethernet VIP product development. Jaspreet received his B.E. degree in Computer Science and Technology, with postgraduate in VLSI.

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