How to Verify ARM ACE Coherent Interconnects with UVM verification IP
The ARM® AMBA® 4 Coherency Extension (ACE™) specification was published last year to satisfy the growing market demand for more performance with less power consumption in today's multi-core systems-on-chips (SoCs).
Cache-coherent interconnect is the key component in any ACE-based SoC. The interconnect plays the role of the coherency manager; for example, the interconnect needs to snoop the right master, calculate the appropriate response, and make sure it returns the correct data. Some interconnects might include more complex operations such as speculative fetches to save time or a snoop filter to prevent unnecessary accesses to processors that might not be sharing data.
Designing a cache-coherent interconnect that will provide the best performance while implementing the complex capabilities needed for cache coherency is extremely difficult; however, verifying it is even more difficult.
This webinar will explain how to build a Universal Verification Methodology (UVM)-based verification environment including verification IP to verify an ACE-based interconnect.
This webinar covers:
- Examples of ACE requirements applied to a reference interconnect
- An analysis of the coherency verification challenges
- Using UVM stimulus, checks, and coverage to verify coherency
- Mimicking memory and processors using active agents
- Using an interconnect monitor to verify correct transmission of data
- Developing a UVM coverage model
Mirit Fromovich, Verification IP Solutions Architect, Cadence Design Systems
Mirit Fromovich, Verification IP Solutions Architect at Cadence Design Systems, leads the worldwide deployment of AMBA verification IP. Mirit is an expert in the application of verification IP and advanced verification techniques and has supported the verification of multiple ACE-based designs. Mirit holds a BSC in software engineering and mathematics from the Bar-Ilan Institute of Technology.