Verifying Advanced Low Power Designs – Why Comprehensive LP Static Checking is Needed Throughout the Implementation Flow
Today’s SoCs—especially devices for mobile applications—must support relentlessly growing system-level power management demands. To provide the needed sophistication and granularity, mobile SoCs use ever more complex advanced low power methodologies. We’ll describe the design implications of these advanced low power techniques, and the static checking capabilities designers need to verify the consistency and correctness of low power intent and implementation through the flow. Then we will look at how some of the new checking and debug capabilities in MVRC can address these requirements, and show a brief use case example.
Director of Product Marketing, Static and Low Power Verification
David has a broad background in EDA and semiconductor marketing, including tools and solutions spanning implementation, verification and manufacturing flows.
R&D Group Director, Low Power Verification
For more than 10 years, Vinay’s focus has been on developing Low Power EDA technologies and products. Prior to Synopsys, he was VP of Engineering for Archpro where he was responsible for developing MVSIM and MVRC products. Vinay also worked at Sequence Design where he served in various engineering and management roles, including VP of R&D for static timing, signal integrity and power integrity analysis products.
CAE Manager, Low Power Verification
For the past seven years, Prapanna has been developing and deploying Low Power verification technologies and products at Synopsys and at ArchPro (acquired by Synopsys). Prior to that, he was Senior R&D Engineer at Texas Instruments, developing software tools for reliability and dynamic IR-drop validation.