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Low Power Video Processing for the Mobile SoC: How Analysis of HW-SW Partitioning Gets the Most from Embedded GPUs

Original Air Date: Oct 18, 2012 | Duration: 60 minutes Webinar
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Overview:
In the highly competitive market for mobile devices, low power video processing is an important criterion for product success. Consumers of the latest smart phones, tablets, and cameras are looking for the best video experience with the least impact on battery life.

To address these challenges, system designers are replacing fixed graphics hardware with the programmability and parallel processing of the embedded multicore GPU, or graphics processing unit. This strategy offloads the main CPU and maps the most demanding video processing tasks to the efficient GPU subsystem.  But important questions remain: How many GPUs cores? Which software mapping provides the best result?

SoC architects can answer these questions early in the design process with solutions from Synopsys. In this webinar, you’ll see how Synopsys Platform Architect is used to efficiently explore and optimize the HW-SW partitioning and mapping of a real-time video encoding algorithm on to an example multicore SoC architecture for both performance and power.

Estimated length:
1 hour including questions

Who should attend:
System Designers, Product Architects, SoC Architects, and Project Managers

What Attendees will learn:

  • Low power video processing for mobile SoCs with embedded GPUs
    • Challenges and opportunities for the architect
    • Why HW-SW partitioning and mapping decisions are key
  • Case study illustration featuring Synopsys Platform Architect
    • How to capture and simulate a system-level performance model of a real-time video encoding algorithm using Virtual Processing Units (VPUs) in SystemC
    • How to analyze the HW-SW partitioning and mapping of the video encoding application on a multicore SoC architecture by examining VPU task and transaction traces, utilization statistics, and memory footprint analysis
    • How to compare mappings and the impact of design parameters (clock frequency, memory latency, bus configuration) on performance and cost metrics, to determine the least expensive design that meets performance requirements

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