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Deploying UVM Effectively: How to Simplify Testbench Debug and Improve Turnaround Time with VCS

Original Air Date: Oct 2, 2012 | Duration: 60 minutes Webinar
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Overview:
In the past two years the number of companies using SystemVerilog testbench with UVM or migrating to UVM has increased dramatically. They are moving to SystemVerilog because coverage, assertions and object-oriented programming concepts like inheritance and polymorphism allow them to reuse code much more efficiently so they can find not only the bugs they expect, but also corner-case issues. They have proven that building testing frameworks that randomly exercise the stimulus state space of a design-under-test and analyze completion through coverage metrics is the most effective way to validate a large chip. UVM offers a standard method for abstraction, automation, encapsulation, and coding practice, allowing teams to build effective, reusable testbenches quickly that can be leveraged throughout their organizations. For all of its value, UVM deployment has unique challenges, particularly in the realm of debugging. Some of these issues are:

  • Phase management: objections and synchronization
  • Thread debugging
  • Tracing issues through automatically generated code, macro expansion, and parameterized classes
  • Default error messages that are verbose but often imprecise
  • Extended classes with methods that have implicit (and maybe unexpected) behavior
  • Object IDs that are distinct from object handles
  • Visualization of dynamic types and ephemeral classes

Debugging even simple issues can be an arduous task without UVM-aware tools. This public webinar will review how to utilize VCS and DVE to most effectively deploy, debug and optimize UVM testbenches.

Presenters:
Rebecca Lipon, Senior Product Marketing Manager, Verification Group, Synopsys
Rebecca Lipon is the Senior Product Marketing Manager for the functional verification product line at Synopsys. Prior to joining the marketing team, Rebecca was an Applications Engineer at Synopsys working on UVM/VMM adoption, VCS, VIP, Magellan and Leda deployments. Rebecca has more than 10 years of experience in the semiconductor industry and has held verification engineering roles at SGI and ATI.

Adiel Khan, Corporate Applications Engineer (CAE), Verification Group, Synopsys
Adiel Khan has been a Verification Specialist in the FPGA and ASIC industry since 2000. He has worked on several interesting projects ranging from packet-based FPGA verification through micro-controller devices, to complex multiple CPU SoC architecture verification. At Synopsys, Adiel works directly with customers to help them develop new verification methodologies.

Amre Sultan, Senior Applications Consultant, Global Technical Services, Synopsys
Amre Sultan has more than 12 years of verification experience, including extensive experience with SystemVerilog, OOP and advanced verification methodologies such as UVM and VMM. Amre is also an active contributor to industry conferences such as DVCon and SNUG. Prior to Synopsys, Amre has worked at numerous semiconductor companies in Ottawa.

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