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Debugging Methods for FPGA-Based Prototypes—Best Practices for System Troubleshooting and RTL Debug

Original Air Date: Sep 18, 2012 | Duration: 60 minutes Webinar
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Overview:
As SoCs continue to grow in size, designers using FPGAs for prototyping find themselves needing wider signal visibility and more debug capacity for complex protocol validation. They require easier ways to transition from the simulator verification environment to an FPGA-based system and alternative ways to model SoC subsystems or interfaces that are not readily available. New methods and technology presented at the seminar will show how to increase the ROI of an FPGA-based prototype and expand its role for hardware/software validation.

This webinar is intended for all designers who are either already prototyping their ASIC design or are considering prototyping their next ASIC design. Learn about best practices and new technology that will increase the productivity of FPGA-based prototypes for hardware/software validation.

What attendees will learn:
  • Best practices for FPGA-based prototype bring-up troubleshooting and RTL debug
  • New technology to increase signal visibility and sample storage of prototypes
  • Connectivity options for prototypes that expand the number of HW/SW validations scenarios supported
Presenter:
Troy Scott, Product Marketing Manager, Synopsys
Troy Scott, product marketing manager, is responsible for FPGA-based prototyping software tools at Synopsys. He has 20 years of experience in the EDA and semiconductor industry. Before joining Synopsys he was a product manager at Lattice Semiconductor, where he worked to design and market FPGA design tools. His background includes HDL synthesis and simulation, SoC prototyping, and IP evaluation and marketing. He holds a BSCE from Oregon Institute of Technology and a Graduate Certificate in Computer Architecture and Design from Portland State University.

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