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How to Make Your SoC Simulation Run 100x Faster with Accelerated Verification IP

Original Air Date: May 30, 2012 | Duration: 60 minutes Webinar
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Overview:
Verification teams commonly find that the large size of their SoCs exceeds the ability of logic simulators to effectively verify them. Simulation acceleration addresses this problem by coupling logic simulation with a hardware accelerator to deliver performance 100 to 1000 times faster than logic simulation. Until recently, the use of simulation acceleration has been limited by the inability to stimulate the design's interfaces at a rate fast enough to keep up with the accelerator.

Cadence now addresses this problem by providing a line of Accelerated VIP (AVIP) supporting several standard interfaces to unlock the inherent speed of simulation acceleration. The AVIP supports multiple user interfaces targeting various stages of product verification. In particular, AVIP enables reuse of simulation test benches based on the popular Universal Verification Methodology (UVM).

This webinar covers:

  • An overview of the current verification methods used to verify, IP, SoCs, and Systems
  • Detailed exploration of simulation acceleration including strengths and limitations
  • The function of accelerated VIP (AVIP) in supporting simulation acceleration
  • The various user interfaces of AVIP, the tradeoffs of each, and the benefits for SoC verification and HW/SW integration
  • Examples of success achieved on real designs

Presenter:
Pete Heller, Senior Product Line Marketing Manager

Pete Heller is Senior Product Line Marketing Manager for SoC/System level Verification IP (VIP) including Interconnect verification at Cadence. With over 20 years industry experience he has played a key role in the growth of Cadence's VIP business. Pete holds both a BA in Computer Science as well as an MBA from Indiana University's Kelley Graduate School of Business.


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