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Faster Clock Constraint Analysis and Debug

Original Air Date: Oct 25, 2011 | Duration: 60 minutes Webinar
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Overview:
Learn how to save time using Galaxy Constraint Analyzer and PrimeTime to ensure clean clock constraints and to keep clocks free of timing violations during signoff. See how these tools work on real designs when used to analyze SDC constraints, identify clock problems, and debug timing violations. Hear expert recommendations for the best flow to analyze and debug complex clock constraints and timing violations.

Clocking schemes and the constraints that drive them are growing in complexity – driven by smaller geometries, larger hierarchical designs, power gating requirements, broader use of 3rd party IP and re-use of internal IP blocks. This increased complexity, often requiring collaboration from CAD and design teams around the globe, can lead to delays in implementation and signoff caused by clock-related violations. This is the first of three application-specific webinars tailored to help you work more efficiently and get results faster.

This 30 minute webinar, including two demonstrations, will be followed by a Q&A session with our Corporate Applications and R&D teams.


Who should attend
Designers & managers responsible for digital IC design, implementation and signoff – especially those responsible for timing constraints, IP integration and final timing closure.

Speakers:

Karen Linser

Staff Corporate Applications Engineer, Implementation Group
Synopsys


Karen is a Staff Corporate Applications Engineer at Synopsys supporting Galaxy Constraint Analyzer. After moving from design into EDA in 2001, she has focused on transistor and gate level static timing analysis. Karen received a BS in Electrical Engineering from the Missouri University of Science and Technology.


Robert Landy
Staff Corporate Applications Engineer, Implementation Group
Synopsys


Robert is a Staff Corporate Applications Engineer on the PrimeTime team. After working in IC CAD and design methodology for mixed signal analysis, he moved into EDA in 2002. Robert has been responsible for providing advanced scripting solutions for clock mesh analysis, SI-enabled design flows and gate-level static timing analysis. He received his Electrical and Computer Engineering degree from the University of South Carolina.

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