Extraction Features and PDKs for Accurate Analog Design
Learn how StarRC new custom design features including 3D symmetric net extraction, optimized PCELL solution, and qualified PDK support, enable accurate and productive analog/mixed-signal design.
This webinar will focus on key topics to accelerate your analog design:
- How to setup StarRC in full custom layout environments using the qualified process design kit (PDK) files from major foundries
- How Rapid3D Fast Field Solver provides performance and accuracy for transistor level flow
- How to handle extraction for digital and analog blocks (with PCELLs)
Who should attend
Design and CAD engineers and managers responsible for parasitic extraction and custom AMS design/layout.
Principal Engineer/Manager, CAE
Krishnakumar Sundaresan is principal engineer and manager of the StarRC Corporate Application Engineering team at Synopsys. Krishna has more than 21 years of combined circuit design and application engineering experience and is responsible for StarRC extraction flow & methodology at both gate level and transistor level. Krishna received his Bachelors of Engineering from National Institute of Technology (MP), India.