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Avoid Electromigration & IR-drop Effects in Custom IP Blocks

Original Air Date: Oct 26, 2011 | Duration: 45 min Webinar
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Overview:
Learn how advances in process technology and changing design styles are increasing the impact of electromigration and IR-drop effects on the performance and reliability of analog, mixed-signal, memory and custom digital IP blocks at 28nm and below. In this webinar, we provide a detailed discussion on the various trends exacerbating EM and IR-drop effects, cover design and analysis techniques to avoid them, and introduce Synopsys’ transistor-level analysis solution, based on CustomSim (FastSPICE), StarRC (extraction) and Custom Designer (custom layout).

The webinar will be followed by a Q&A session with our Corporate Applications and R&D teams.

Speakers:
Bradley Geden
Solution Architect

Bradley is a Solution Architect for Synopsys’ Analog/Mixed-Signal business unit responsible for assembling solutions that address custom design and verification challenges. He has over 15 years of experience in the EDA and semiconductor industries. Bradley started his career as an analog/mixed-signal IC design engineer at the SAMES foundry in South Africa and subsequently joined CML Micro in the UK where he was responsible for leading IC design teams delivering products for the wireless and wire-line markets. His career in EDA has spanned various technical and product marketing positions at both Mentor Graphics & Synopsys. Bradley received his bachelor degree in electronic engineering from the University of Pretoria in South Africa.

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