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Learn to Analyze, Validate and Debug High Speed DDR3 Memory Webcast

Original Air Date: Oct 4, 2011 | Duration: 60 minutes Webinar
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Overview:
This Webcast will demonstrate techniques and solutions for performing turn-on, interoperability, validation and compliance testing of high data rate DDR3 memory based products. Explore case study examples covering debugging of intermittent initialization, functional validation, and cross triggering to gain faster and more complete understanding of memory issues. Learn about time saving bus level signal integrity insight and how to setup triggers on specific events of interest to capture traces that help you see and understand problems in your DDR3 systems.

Who should view this webcast:
This webcast would be of interest to R&D Engineer, validation and systems integration teams performing turn-on, interoperability, validation and compliance testing of high data rate memory based products & Digital Design Engineers.

Presenters:
Jennie Grosslight, Product Manager, Agilent

Jennie Grosslight is the product manager of Agilent's Digital Debug Solutions memory solutions where she is responsible for Agilent's logic analysis and compliance test tools for Memory applications. Jennie has worked more than 20 years at Hewlett Packard and Agilent Technologies in a variety of roles for both Oscilloscopes and Logic Analyzers, including R&D engineer, Technical Marketing Engineer, and product marketing. Jennie has been focused on helping customers analyze and validate memory systems for the past 6 years. She has a degree in Electrical Engineering from the University of Colorado at Colorado Springs.

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RBest Posted Oct 4, 2011

where can I get the PDF of your presentation ? thank you...

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