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Divide and Conquer: Faster FPGA Delivery using Hierarchical, Parallel Design Development

Original Air Date: Sep 20, 2011 | Duration: 60 minutes Webinar
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Overview:
With the arrival of FPGAs that deliver in excess of twenty million equivalent ASIC gates, the design of programmable devices is evolving. Designs have expanded into projects involving multiple design file sources, each in various stages of evolution. Such designs may involve distinct hardware design teams, software development teams and verification teams located in the same building or around the globe, each trying to make progress in parallel on the design.

Divide-and-conquer!
In this 1 hour webinar, technical experts from Synopsys will offer tips on how to effectively deploy hierarchical design approaches during FPGA logic evolution. Topics covered will include how to:

  • Perform parallel development—From farming the design out to multiple machines to distributing the tasks across design teams
  • Improve previous designs quickly using bottom-up flows or hybrid top-down/bottom-up flows
  • Deal with the complexity of hundreds or thousands of source files
  • Precisely tweak performance and isolate bugs while preserving working parts of the design—How not to upset the apple cart!
  • Accommodate the design team's development process—Synchronize software development, hardware development and verification

If you are embarking on large-scale FPGA SoC design, you won't want to miss this informative webinar.

Presenter:
Angela Sutton, Staff Product Marketing Manager, FPGA Implementation
Angela Sutton brings over 20 years of experience in the field of semiconductor and semiconductor design tools to her role as staff product marketing manager for Synopsys, Inc. In this role, she is responsible for the FPGA Implementation product line.

Prior to joining Synopsys, Ms. Sutton worked as senior product marketing manager in charge of FPGA Implementation tools at Synplicity, Inc., which was acquired by Synopsys in May 2008. Ms. Sutton has also held various business development, marketing and engineering positions at Cadence, Mentor Graphics, Responsys, and LSI Logic. At LSI Logic she was responsible for marketing LSI Logic's line of digital video semiconductor products and platforms.

Ms. Sutton holds a BSc. in Applied Physics from Durham University UK, and a PhD. in Engineering from Aberdeen University, UK.

11 comments
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Massoud.Emdadian Posted Sep 20, 2011

To whom it may concern, Hello, I would like to further email contact and discuss with Ms. Sutton about an specific question on the difference between the hard block definition and soft block definition of the RTL moduls... With this also I would like to thank her for an excellent presentation. Kind Regards, Massoud Emdadian, CEO/CTO Dmtron.com massoud.emdadian@dmtron.com

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joanedoned Posted Mar 26, 2014

I am in the same situation and I want to see more about this topic!

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joanedoned Posted Mar 26, 2014

yes, he has, I found many top quality articles on this website and for sure he will publish more!

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pois Posted Feb 4, 2014

t has been informed that with the arrival of FPGAs , the delivery system has been speed up n excess of twenty million equivalent ASIC gates.The webinar by several experts have made us understood the need to adopt FPGAs. powered.com

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