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Xilinx FPGA Design Using RTL-based projects with PlanAhead Design and Analysis Tool

Original Air Date: Jul 26, 2011 | Duration: 60 minutes Webinar
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Overview:
Xilinx FPGAs are currently designed using the ISE design suite of tools, which allow design entry, synthesis, verification, and implementation functions to generate a working bit file. Traditionally, Project Navigator is the graphical front end (GUI) tool which users use to create and manage projects and execute compilation flows to generate a bit file. PlanAhead is an alternative tool that can be used in a similar capacity and offers a number of advantages. These advantages include easy-to-use and powerful pin planning, floorplanning, design analysis and debug capabilities.

This webinar will go into technical depth on the use of PlanAhead for designing Xilinx FPGAs. We will guide you through creating a design using RTL design entry, utilizing Xilinx IP Repository, verifying functionality with ISE Simulator, synthesizing with XST, IO assignment, inserting debug logic for ChipScope, implementing the design with various tool option strategies, floorplanning for timing closure, generating a bitstream file, and launching iMPACT and ChipScope Analyzer to program and debug a device.

What Attendees with Learn:
  • How Xilinx FPGAs can be developed using PlanAhead with RTL-based projects.
  • RTL design entry, text editing, debug and cross-probing
  • IP customization, generation, and instantiation in RTL
  • Simulation using ISESim
  • Launching RTL synthesis and understanding strategies.
  • Simple IO pin assignment and floorplan physical constraint creation.
  • Assigning nets to be debugged using ChipScope analyzer
  • Launching implementation and analyzing results.
  • Launching XPower Analyzer and FPGA Editor and using cross-probing.
  • Generating a bit file.
  • Launching iMPACT and ChipScope Analyzer.
Who Should Attend:
  • FPGA designers who are starting new FPGA designs using Xilinx ISE Design Suite tools.
  • FPGA designers who are interested in more efficient work flows using advanced tools.
  • FPGA designers who have used PlanAhead for pin planning, floorplanning, or design analysis capabilities.
  • FPGA designers who have used Project Navigator to design projects and used PlanAhead through Project Navigator integration modes.
Presenter:
Greg Daughtry, Senior Product Marketing Manager, Xilinx
Greg Daughtry holds the position of senior product marketing manager responsible for PlanAhead overseeing all aspects of product design phases: definition, development, and roll-out. He has over 16 years of experience in the hardware and software industries. Mr. Daughtry was most recently an ASIC design engineer developing advanced EDA tools methodology at Avago Technologies. Prior to that, he worked in the capacity of field sales and applications engineering at EDA startups Sierra Design Automation, which was acquired by Cadence and Monterey Design Automation, acquired by Synopsys. Both of these companies produced advanced EDA tools for ASIC floorplanning, placement, physical synthesis, routing, static timing analysis and verification. Prior to this, he worked at Intel as a full-custom circuit design engineer on multiple generations of leading-edge microprocessors and a signal integrity engineer for high-volume motherboards and chipsets. Mr. Daughtry also has worked at several startups a software engineer doing Graphical User Interface (GUI) design, enterprise peer-to-peer client/server transaction infrastructure, and industrial control and automation. He holds a B.S. in Electrical Engineering and a B.S. in Computer Engineering, and a M.S. in Computer Engineering, all from North Carolina State University.

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