Meeting Aggressive Power Budgets with Xilinx 7 Series FPGAs
Engineers tasked with architecting the latest electronic systems are faced with a set of ever-increasing and conflicting challenges: increasing integration and performance while reducing form factor and cost. All of these pressures require greater attention to the management of power consumption and thermal dissipation. Judicious component selection and techniques for power optimization are becoming critical to successful, high-performance, power-efficient system designs.
Through a versatile 28nm High Performance Low Power (HPL) process and a unified and scalable architecture, Xilinx is able to deliver a full range of power-efficient FPGA product families for today's demanding applications. Xilinx 7 series FPGAs ensure that system designers can achieve power-optimized designs while meeting critical performance targets. In this webcast, we explain the process choices, device architecture and circuit techniques Xilinx has employed to accomplish these goals. We review several in-depth case study examples to illustrate how Xilinx tools, design techniques, product features, and new device options can enable engineers to apply these power and performance advantages to their unique FPGA-based designs.
Who Should Attend:
Hardware system designers, system architects, project managers, and PCB designers
What Attendees will Learn:
- How Xilinx, through a versatile 28nm High Performance Low Power (HPL) process and a unified and scalable architecture, is able to deliver a full range of power-efficient FPGA product families for today's demanding applications
- How designers can leverage the latest Xilinx tools, design techniques, product features, and device options to achieve power-optimized designs while meeting critical performance targets
- FPGA designers who want the latest information from Xilinx on optimizing power and performance in their designs
- ASIC designers migrating to FPGAs who need to meet aggressive power targets
- Systems engineers dealing with cost / power / performance tradeoffs
Matt Klein, Principal Engineer, Applications and Technical Marketing Group, Xilinx
Matt is a principal engineer in the applications and technical marketing group at Xilinx. Matt continuously works with customers, IC Design, Product Test Engineering, and Xilinx Technology Development to bring the lowest power to Xilinx customers and Xilinx products. He has worked at Xilinx for 7 years and has worked with FPGAs for > 20 years having done close to 50 FPGA designs and worked on system architectures of several large products. Matt has a B.S.E.E from Case Western Reserve University and an M.S.E.E. from Santa Clara University.
Peggy Wu Abusaidi, Senior Product Marketing Manager, Silicon Marketing Group, Xilinx
Peggy Wu Abusaidi is a senior product marketing manager in the silicon marketing group at Xilinx. Prior to Xilinx, she had over eleven years of experience at AMD, Inc., holding positions in product engineering for SRAM products and product marketing for Bus Interface controller, SCSI, SCC, Ethernet MAC, Repeater, and Switch controller products. She holds a Master of Engineering Management from Santa Clara University and a Bachelor of Electrical Engineering from the University of California, Berkeley.