Maximizing off-chip memory performance, the great CPU and GPU balancing act
Efficient access to shared off-chip memories, especially DRAM, critically influences system performance, power and cost. The available bandwidth to main DDR memory is often the system performance bottleneck. Higher utilisation of bandwidth allows the use of lower frequency memories, with cheaper packaging and narrower ports reducing the number of high performance DDR PHYs. DRAM controllers must also be designed for optimal efficiency with CPU and GPU requirements in mind. Minimising CPU latency is a critical requirement, at the same time as maximising available GPU bandwidth. Balancing system QoS requirements at the same time as maximising memory utilisation is a difficult challenge. This webinar will explain the critical success factors in building processor-to-pads memory systems that meet the demands of complex, high performance SoCs.
- Advanced memory subsystems are becoming vitally important for SoC design
- ARM is a leading expert in memory controller and PHY technology
- CoreLink DMC-400 is the first AMBA 4 memory controller
- Best in class memory utilization
- Scalable microarchitecture provides roadmap to future memory types: LPDDR3, DDR4 and Wide-IO
- ARM has a processor-to-pads system solution with end-to-end QoS
Tom Conway, Staff Engineer, ARM
Tom Conway is currently one of the technical leads for the development of new memory controllers at ARM. He is an expert in all aspects of memory controllers, having experience in RTL design, verification and FPGA system validation of ARM's static and dynamic memory controller products. Tom has been at ARM, working on system IP Products, for 7 years since completing his Electronic Engineering degree at Imperial College London.