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Optimize power and performance with Artisan 40nm physical IP

Original Air Date: Apr 19, 2011 | Duration: 60 min Webinar
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Overview:
Discover best-in-class strategies for designing optimized SoCs using silicon proven ARM® Artisan® Physical IP for TSMC's 40nm G / LP manufacturing processes. During this webinar, we will demonstrate cost-effective techniques for designing performance driven consumer devices requiring advanced functionality without increasing power consumption. We will also discuss how to enable higher levels of technology innovation, while maintaining power budgets in performance driven consumer devices such as disc drives, set-top boxes, mobile computing devices, networking applications, high-definition televisions and graphic processors.

The session will cover how to:
  • Obtain a high degree of flexibility through multi-channel Logic libraries
  • Enable significant power and cost savings by replacing or complementing the HVt, RVt or LVt implant layers with long channel length devices providing better performance, lower leakage and reduced manufacturing costs.
  • Utilize advanced embedded memory compilers and interface IP to meet a wide range of performance, power and area requirements.
  • Reduce both dynamic and leakage power in SoC designs
  • Leverage superior ARM CPU implementation with Artisan high-density memories, innovative high-speed architecture, and multiple processor-specific low power management modes.
Attend this webinar to gain a thorough understanding of:
  • Best-in-class practices for managing your power and performance envelopes
  • Benefits of ARM's Artisan 40nm G IP platform
  • Effective methods of leveraging ARM processor and physical IP for superior ARM CPU implementation
Who should attend?
  • Design engineers and team leads designing SoC on TSMC 40nm process.
  • Embedded memory design teams
Presenter:
Leah Schuth, Manager Technical Marketing, Physical IP Division, ARM
In her role, Leah is the Manager of Technical Marketing for the Physical IP division, a position she has held for the past year. Prior to that, Leah was the Technical Marketing Manager of Logic Products for three years.

One focal point of Leah's work is enabling successful customer evaluations and adoption of PIPD products, through internal and external interactions with engineering and marketing teams. Two examples of focused products are the Power Management Kit (PMK) and the Multi-channel libraries. Both products enable implementation of power management techniques in chip designs, and the PMK specifically has allowed Leah to work closely with the leading EDA providers to ensure that ARM Physical IP and the low power features within the EDA tools work together.

Leah holds a B.S. in EECS from the University of California, Berkeley.

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