Functional Verification Webinar Series
Advance Your Functional Verification Skills with Cadence Technical Webinars
Join Cadence® verification experts for a series of technical webinars on the most relevant topics in functional verification. We'll introduce you to the latest techniques, best practices, methodologies, and support services you need for designing and verifying your silicon designs.
In these concise, 1-hour sessions, our technical experts will address hot topics including the Universal Verification Methodology (UVM), low power, metric-driven verification (MDV), formal techniques, and mixed-signal verification approaches. Choose from either introductory or application-specific webinars that will help you streamline your verification process.
- Discover possible solutions and best practices to tackle your toughest verification problems
- Learn new applications and methodologies to boost productivity and profitability
- Ask questions and get the answers you need to adopt new approaches
- Follow up with our technical field experts and hone your skills using the Incisive Verification Kit
These webinars are designed to be methodology- and application-based, not a marketing pitch. Plus, you don't need to travel—you can view these presentations and demonstrations from the comfort of your home or office!
Cadence Functional Verification Webinar Topics – Helping You Achieve Silicon RealizationIntroductory Webinars
- March 17, 10:00am PDT - Building Automated and Reusable Testbenches using the SystemVerilog UVM
- April 14, 10:00am PDT - How to Successfully Verify Your Low-Power Designs
- March 24, 10:00am PDT - How to Completely Eliminate SoC Connectivity Bugs (Really!)
- April 21, 10:00am PDT - Improve verification productivity by 40% with Specman Advanced Option
- May 12, 10:00am PDT - Verification 1-2-3 with Assertion-Driven Simulation
- May 26, 10:00am PDT - Creating Meaningful Verification Plans
- June 16, 10:00am PDT - Reuse Legacy VMM VIPs in the UVM in 6 Simple Steps
- June 23, 10:00am PDT - Verifying and Modeling Registers Using the SystemVerilog UVM