Breakthrough in High Speed Interconnect Analysis and Compliance Testing
As bit rates of digital systems increase, signal integrity of interconnects, transmitters & receivers drastically affects system performance. To ensure product reliability, compliance test specifications for high speed serial technologies become more complicating with multiple and yet strict measurement requirements on TDR, S parameter, and eye diagram. As a result, it is more challenging to have successful design for the next and deliver high standards to meet customer's needs. In this session, we introduce new Agilent ENA Option TDR, a one-box solution that provides breakthroughs to traditional measurement solutions, which enables to address digital engineers advanced access and efficiency to signal integrity design and verification. The contents are delivered with real case studies from the contemporary compliance specifications.
Who should view this webcast:
- Digital engineers who deal with design and verification for high speed digital applications and devices
- Test engineers who perform compliance testing according to compliance specifications
- Engineers and operators who use TDR oscilloscopes for TDR, S parameter, and eye diagram measurements.
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Hidekazu Manabe, Application Marketing Engineer
Hidekazu Manabe joined Agilent Technologies in 2002. He started his career as a technical support engineer for vector network analyzers, impedance analyzers, and LCR meters. Since 2008, Hidekazu has been engaged in application development for high speed digital standards. With expertise in TDR and S parameter measurements, He is a member of USB-IF, HDMI, VESA, SATA-IO to discuss the latest specifications and propose to the committees the appropriate solutions for electrical measurements on cable/connector and transmitter/receiver compliance testing.
Andrew Baldman, Senior Technical Staff Member at the University of New Hampshire Inter Operability Laboratory
Andy has been with the UNH-IOL since 1997, where he began his career as an undergraduate Electrical Engineering student, performing and developing physical layer testing for 10/100/1000 Ethernet. As a graduate student he developed UNH-IOL physical layer test suites and software for the 10G Ethernet XAUI and 10GBASE-CX4 specifications. Andy became a full-time staff member in 2002, and has since developed the IOL's physical layer test suites for SAS and SATA, and has authored several Method of Implementation (MOI) documents for the SATA-IO Interoperability Test Program. He has extensive experience with MATLAB, and has written custom test automation software for many makes and models of DSOs, TDRs, VNAs, and signal generators. He is also the author of the MIPI Alliance D-PHY and M-PHY physical layer conformance test specifications, and currently leads the UNH-IOL's SATA and MIPI test efforts.