PCI Express(R) 3.0 Strategies for Transmitter and Receiver Validation
PCI Express (PCIe™) is the I/O technology of choice in high performance desktop and server applications. PCIe technology offers the benefits of reduced power consumption, scalability of bandwidth, increased data throughput and improved signal integrity. PCI Express signaling is continuing to deliver segment leading performance and data throughput, moving to 8GT/s. Increasing its data rate well beyond PCIe 2.0 speeds, PCI Express 3.0 presents many new challenges to the industry. For example, at 8GT/s places a significant burden upon the physical channel, transmitter, and receiver. Signal integrity, while important will all generations of PCI Express technology, becomes a crucial component of any PCIe 3.0 design. and signal integrity design and validation. In addition, the migration to a 128/130 bit encoding scheme for PCIe 3.0 creates additional challenges in physical layer validation as well as logical validation.
This presentation will provide you with an overview of the latest developments in the PCI Express 3.0 standard, including new methods for validating transmitter jitter, transmit de-emphasis and preshoot, equalization parameters, and the effects of de-embedding on PCI Express compliance measurements. We will also discuss key considerations for receiver jitter stress testing at both the component and system level.
Who should view this webcast:
Engineers involved in high speed serial communications design in the computer or related digital industries, signal integrity engineers, IC designers, validation engineers working on physical layer transmitter and receiver validation and conformance to specification or debug.
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*PCI EXPRESS is a registered trademark of the PCI-SIG
*PCIe is a trademark of the PCI-SIG
Rick Eads, Agilent Technologies
Rick is a senior product manager at Agilent Technologies and serves on the PCI-SIG Board of Directors, contributing to the Electrical, CEM and Serial Enabling work gro