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Power Reduction in Next-Generation UltraScale Architecture

Authored on: May 1, 2014 by Srinivasa Kolluri

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With the Xilinx UltraScale architecture, designers can take advantage of enhanced power reduction technology built into the Kintex and Virtex families, based on the industry's first ASIC-class  programmable architecture. Xilinx has continued to study and implement many different power reduction strategies, which span process changes and improvements, architecture changes, voltage-scalable products, and software power-optimization strategies. In planning UltraScale devices, all of these strategies were evaluated based on their impact on static power, dynamic power, and I/O power. Read this white paper to learn more.

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