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Hierarchical Testbench Configuration Using UVM

Authored on: Jun 3, 2014 by Hannes Nurminen, Satya Durga Ravi

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Verifying today's complex SoC poses a significant challenge.  Use of a robust and reusable testbench that leverages proven methodologies can significantly improve the efficiency of verifying the different configurations of the SoC. This paper focuses on the use of Accellera Systems Initiative's Universal Verification Methodology (UVM) to create a scalable, robust and reusable test environment.
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