Novel CMOS Device Designs for Low Power Microelectronics
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The design and electrical characteristics of novel NMOS and PMOS composite devices that eliminate the momentary short circuit currents that flow during the logic transitions of CMOS logic gates are examined. These novel devices significantly reduce the switching noise and power dissipation in CMOS logic circuits without adversely impacting integration packing densities and with relatively minor impact on overall circuit speeds. CMOS logic gates designed with these novel devices have extended noise margins, the extended noise margins generally associated with Schmitt triggers, thereby enhancing the tolerance of the CMOS circuit to noise. This paper describes the novel device concepts and validates their effectiveness.